A low dropout (LDO) regulator is a DC linear voltage regulator, and it is used to maintain a constant voltage in several electronic devices. For example, multiple LDO regulators are present in a system on chip (SOC) environment. Each IP block and/or individual function of the SOC may have a dedicated reference voltage generator, which generates a bandgap reference voltage, and a constant voltage output from the dedicated reference voltage generator is maintained by one or more LDO regulators. Furthermore, the number of LDO regulators in the SOC may increase rapidly due to popularity of new capless LDO regulators and high demand for block to block noise isolation in the SOC.
Currently, the LDO regulator is being tested using one of two known methods. First, as illustrated in FIG. 1, a conventional non-BIST scheme uses a test device 112 such as a voltmeter to measure LDO regulator outputs present in each IP block through a test port 110 (e.g., an external pin of a SOC 102). Accordingly, this scheme may require several external ports to measure the LDO regulators (e.g., LDO 104A through LDO 104N) present in the IP blocks of the SOC 102. During the process, outputs (e.g., V 106A through V 106N) from the LDO regulators are multiplexed using an M-to-1 MUX 108 and forwarded to the test device 112 through the test port 110. As a result, it may be time consuming for the test device 112 to obtain data through the test port 110 which often employs joint test action group (JTAG) interface.
FIG. 2 illustrates a conventional BIST scheme to test LDO regulators 224 present in an SOC 202. There may be several BIST circuits including a BIST circuit 204A in the SOC 202 connected to a test device 206 through at least two test ports (e.g., a test port 212 and a test port 214). A calibration signal (e.g., VCAL 210) from the test device 206 is used to calibrate the BIST circuit 204A. The BIST circuit 204A may generate a test output 228 by comparing an external reference voltage (e.g., VREF 208) with an output of the LDO regulator 224 using a comparator based on a PMOS 216 and an NMOS 218. The output of the comparator is processed through a buffer 226 to synchronize the test output 228 with other test outputs.
As illustrated in FIG. 2, the conventional BIST scheme requires two test ports (e.g., the test port 212 and the test port 214) to convey two external signals (e.g., VREF 208 and VCAL 210) from the test device 206 to the gate of the PMOS 216 and to the gate of the NMOS 218, respectively. Accordingly, two external pins of the SOC 202 may have to be allocated. In addition, the BIST circuit 204A may require calibration to eliminate non-linearity in the design of the BIST circuit 204A. The extra calibration step may prolong the process of testing LDO regulators 224. For example, it may take approximately 48 ms to complete testing using the conventional BIST scheme of FIG. 2 equipped with 1 MHz clock. Furthermore, the conventional BIST scheme is able to measure only absolute value measurement of outputs of the LDO regulators 224, but does not address the need to perform DC load regulation measurement.